Job Description :
RTL Design Principal Engineer
Phoenix, Arizona/San Francisco CA
12 months
Contribute to the development of efficient Architectures and contribute to ASIC Architecture, design and verification
Understand our in house IPs needed and how they need to be integrated, connected and verified
Drive the top level Architecture definition and develop the necessary RTL
Drive the chip level integration and verification plan development
Supervise the RTL to GDS flow and assist with synthesis and timing closure
Support the test program development, chip validation and chip life until production maturity
Work with FPGA engineers to perform early prototyping
Support hand off and integration of blocks into larger SOC environments
Assist with Algorithm analysis, verification and improvement
Contribute to ASIC digital architecture, design and verification
Basic Qualifications
Bachelor's Degree in Electrical Engineering or equivalent (12 years) work experience (If an, Associate's Degree with 6 years of work experience)
7 years of experience as a Digital Design Engineer and or a Chip Lead
5 years of experience in uP and or GPU and or Video Processing
Preferred Qualifications
Experience in RTL Register Transfer Level coding, synthesis and or SoC System on Chip
Integration Experience in digital design Architecture
System Verilog OVM UVM Python or similar scripting
SoC integration and ASIC architecture
DFT Testability requirement and test program definition
High Speed interfaces like PCIe, USB, MIPI

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