Job Description :
Physical Design Staff Engineer
Phoenix, Arizona
Job Description
Develop own physical design implementation of multi hierarchy low power designs including physical aware logic synthesis, design for testability, floor plan, place route, static timing analysis, IR Drop, EM, physical verification in advanced technology node
Resolve design flow issues related to physical design, identify potential solutions, drive execution
Deliver physical design of an end to end IP or integration of ASIC SoC design
Basic Qualifications:
Minimum of 1 - 3 years of experience in any of the following:
RTL2GDSIIon advanced technology nodes (7nm and below)
Low power implementation and signoff, power gating, multiple voltage rails, UPF/CPF.
Block-level and Full-chip floor-planning and power grid planning.
Python, TCL, or Perl programming.
EDA tools like DC/Genus, ICC2/Innovus, Primetime, Redhawk/Voltus or Calibre
Bachelor's Degree or equivalent work experience (12 years) or an Associate's Degree with 6 years of work experience.
Preferred Qualifications:
Experience running physical aware logic synthesis and achieving optimal synthesis QoR on low power designs
Knowledge of static timing analysis and concepts, defining timing constraints exceptions, corners voltage definitions
Experience with custom or regular clock tree synthesis implementation at block level or top level, clock power reduction techniques
             

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