Job Description :
SoC Emulation Engineer
San Francisco Bay Area, CA
Long Term
Level: CL10 - CL8 (L1 & L2)
Job Description:
- 1-7 years of experience
- Port ASIC/IP RTL to Emulation platforms (Preferred: Zebu/HAPS)
- Build model from released RTL .
- Generate target platform loadable image(s) test and release the image to Firmware and DV teams.
- Run sanity tests for qualifying release of the image(s)
- Release the model to various team including Functional Validation team, Firmware, DV
- Assist debug of failures providing instrumented model ( Waveform Dumps, in circuit debug) and interfacing with stakeholder.
- Coordinate with Tools team to validate tool and Model release
- FPGA and Emulator flows and methodologies
- Experience with Daughtercards, Speedbridges, Virtual Prototyping
- Hardware emulators, such as ZeBu/Palladium or HAPS/Protium
- Emulation methodologies, including in-circuit emulation, hybrid systems, or simulation acceleration
- C and C++ good programming skills.
- Scripting in Python, Tcl, or Perl
- Hardware Emulation Platforms and tools
- Strong knowledge of Complete Design Cycle to understand the Different IP designs to integrate In the build
- Simulation acceleration knowledge (DPI and Transactors)
- In depth understanding of RTL and Synthesis
- Logic simulation: VCS/NCSIM
- Programming/scripting skills (C, C++, Python)
Thanks & Regards
Mohammed Shoaib
Sage IT Inc.
Email: