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Remote - Sr. FPGA HAPS DESIGN ENGINEER
Santa Clara, CA
Santa Clara
CA
95056
Date
: Feb-10-21
2021-02-10
2022-02-10
Remote - Sr. FPGA HAPS DESIGN ENGINEER
Santa Clara, CA
Feb-10-21
Work Authorization
US Citizen
GC
H1B
EAD (OPT/CPT/GC/H4)
Preferred Employment
Corp-Corp
W2-Permanent
W2-Contract
1099-Contract
Contract to Hire
Job Details
Experience
:
Architect, Senior
Rate/Salary ($)
:
Market
Duration
:
Sp. Area
:
C, C++, Middleware, Embedded
Sp. Skills
:
Firmware
Permanent Direct Hire
FULL_TIME
Direct Client Requirement
Remote Work from Home
Required Skills
:
FPGA, HAPS, PROTOTYPING, SOC, VIDEO
Preferred Skills
:
HAPS, FPGA,
Domain
:
Work Authorization
US Citizen
GC
EAD (OPT/CPT/GC/H4)
H1B
Preferred Employment
Corp-Corp
W2-Permanent
W2-Contract
1099-Contract
Contract to Hire
Job Details
Experience
:
Architect, Senior
Rate/Salary ($)
:
Market
Duration
:
Sp. Area
:
C, C++, Middleware, Embedded
Sp. Skills
:
Firmware
Permanent Direct Hire
FULL_TIME
Direct Client Requirement
Remote Work from Home
Required Skills
:
FPGA, HAPS, PROTOTYPING, SOC, VIDEO
Preferred Skills
:
HAPS, FPGA,
Domain
:
HPC AMERICAS
Danville, CA
Post Resume to
View Contact Details &
Apply for Job
Job Description
:
Sr. FPGA HAPS DESIGN ENGINEER- FULL TIME !!
Hiring manager is looking for a Lead who can:
Interface with their customers
Drive the Development platform
Has Prototyping experience
Has done Implementation of SoC in FPGA platform
Has some Video, display exp
Exp in Design, Verification
Have HAPS experience-
Responsibilities:
Develop FPGA designs and subsystems (involving ASICs), from concept to product including:
Completing implementation in RTL, RTL/netlist verification and evaluating Xilinx Vivado synthesis and P&R results for performance and cost
Balancing performance, area, power, complexity and timing
Working closely with firmware and verification teams during specification, development, Integration and Verification phases and deliver working FPGA platforms
Skills:
Experience with RTL Development using Verilog, System Verilog, VHDL
Experience working on FPGA Design projects, including work with SOC (ARM/RISC-V CPU based), MIPI, XAUI, USB, Flash, SDIO, PCI-E, and DDR# Interfaces.
Familiarity with Synopsys (HAPS, Proto-Compiler) OR Xilinx tools/IPs for FPGA Design and implementation.
Coding, debugging skills on both UVM and FPGA Platforms
Knowledge of Debuggers like Lauterbach, J-Link, ARM-DS, Testers & Scope.
Experience in one or more of the following domains: CoreSight, SoC-400, SoC-600, OCP, AXI, ACE, AHB and APB
Familiarity with revision control concepts and tools (e.g. Subversion
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