Job Description :
Role: Design Verification Engineer Location: Sunnyvale, CA Rate: $80 max Remote/Onsite: Day One onsite Hiring Type: TP End Client: Google, Facebook, Cisco, Intel No of postions: 10 Note: In case you get a remote profile feel free to share that as well Mandatory : UVM minimum 3 years of experience also share a write up along with the submission Must be proficient with : Building a test bench for a block using System Verilog and UVM Writing random tests, directed tests, error tests & performance tests for a block of Verilog and UVM. Developing, maintaining and supporting of the UVM verification environment. Debugging tests with design engineers to deliver functionally correct design blocks writing & analyzing functional coverage, assertions Generating and analyzing code coverage & writing waivers

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