Job Description :

“I am looking for a candidate to design and verify a small block to start immediately. The initial contract will be for 18 months,  SOC verification tasks

Job Description:

·         Design a small logic block using Verilog

·         Verify block using stand-alone UVM testbench

·         Integrate block in SOC and verify block in SOC testbench

Must-have Skills:

·         Verilog, SV/UVM, C/C++

·         Recent experience with designs containing AXI4

·         Recent experience with design in Veriloig

·         Recent experience with block/unit level verification using UVM


Nice-to-have Skills:

·         Experience with chip/System level verification

·         Scripting”


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