Job Description :
VERFICATION ENGINEER
LONG TERM CONTRACT 12/2017
IRVINE, CA
1st Phone interviews then final will be Skype.
Verification engineer with experience with Cadence tools and proficiency in System Verilog, UVM and scripting languages
Looking for a senior verification engineer to work as part of HDD SOC development team on next generation Controllers
Responsibilities
- Develop and implement a Cadence vManager-based verification and regression management system including automated coverage merging, analysis, report generation etc
- Support the verification team throughout SOC project phase on the regression management system
- Work as part of a verification team to develop an SV UVM test platform and testing
Skillset
- System Verilog UVM
- Cadence HDL simulators and debuggers
- Prior experience with Cadence vManager preferred
- Scripting – Perl, Tcl
Thanks
Abhishek