Job Description :
Design Verification – Sr. Staff Eng. 4-7yrs of exp. CL8

We´re looking for SoC Design Verification Eng. to provide design verification services for multi CPU/DSP SoC



RESPONSABILITIES:

Testbench devel. - System Verilog UVM and C tests
Integration/devel. of C tests/APIs and SW build flow, UVM mailboxes and HW/SW communication components
Integr. of lower level UVM testbenches
Test plan devel.
Power Aware testbench devel. and simulations
Seamless porting between simulation/emulation/prototyping platforms
Regression setup and debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto
Coverage collection and closure
Working w/ cross functional teams (DV/Arch/Design/FW) to identify coverage scope


MIN. QUALIFICATIONS:

5+ yrs of exp. in RTL Design and Verification area of which 2+ yrs of exp. in SoC Design Verification and HW/SW verif.
Deep knowledge of System Verilog UVM and vertical testbench integration
Knwl of low level HW/SW interaction and debug and multi CPU and debug arch.
Exp. w/ devel. of fully automated flows
Preferred Qualification:
Exp. w/ low level SW debug - disasm, Tarmac,trace,w/ coresight arch., w/ embedded SW low level concepts and debug - Tarmac,ROM,RAM,linkers,elf,disasm, code sections, cache, security, w/ coverage merging across simulation and emulation. Exp. w/ Power Aware and Gate Level Netlist in Emulation, w/ devel. of fully automated flows, w/ Gate Level Simulations
Python Scripting.