RTL Verification Engineer

Sunnyvale, CA Sunnyvale CA 94085

Date : Today (Dec-03-25)

RTL Verification Engineer

Sunnyvale, CA

Today (Dec-03-25)

Work Authorization

US Citizen
GC
H1B
EAD (OPT/CPT/GC/H4)

Preferred Employment

Corp-Corp
W2-Permanent
W2-Contract
1099-Contract
Contract to Hire

Job Details

Experience

:

Architect

Rate/Salary ($)

:

$60K-140K/ Year

Duration

:

12 Months with extensions

Sp. Area

:

Python, Open Source

Sp. Skills

:

x-Other

Consulting / Contract

Required Skills :

Python, Perl, UVM

Preferred Skills :

Domain :

IT/Software

Work Authorization

US Citizen
GC
EAD (OPT/CPT/GC/H4)
H1B

Preferred Employment

Corp-Corp
W2-Permanent
W2-Contract
1099-Contract
Contract to Hire

Job Details

Experience

:

Architect

Rate/Salary ($)

:

$60K-140K/ Year

Duration

:

12 Months with extensions

Sp. Area

:

Python, Open Source

Sp. Skills

:

x-Other

Consulting / Contract

Required Skills :

Python, Perl, UVM

Preferred Skills :

Domain : IT/Software

Apply Now

DMS Vision, Inc.
Frisco, TX
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Job Description :

Position: RTL Verification Engineer || Onsite Sunnyvale, CA (Local is great but relocation is ok)

Location: Onsite Sunnyvale, CA (Local is great but relocation is ok)

Duration: 12+ month project

Visa: USC/GC

Job Description

We are seeking talented RTL Engineers to join our team in Sunnyvale, CA. This is an exciting opportunity to work on cutting-edge digital designs and ensure their quality through advanced verification methodologies.

What You ll Do:

Develop comprehensive verification plans based on micro-architecture and design specifications
Architect and implement reusable, scalable verification environments using SystemVerilog/UVM
Create and run constrained-random and directed tests to achieve high functional and code coverage
Analyze simulation results, identify complex failures, and collaborate with design teams to resolve issues
Build and maintain automation scripts (Python/Perl) to enhance verification workflows and regression management

What We re Looking For:

Strong hands-on experience with SystemVerilog and UVM
Minimum 7 years of verification experience in digital design
Deep understanding of digital logic design and verification methodologies
Experience verifying digital systems with standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems)
Ability to work independently and provide technical feedback to RTL design teams
Proficiency with industry-standard EDA simulation and debug tools
Strong debugging and root-cause analysis skills
Scripting experience in Python or Perl

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