Job Description :
Title: RTL/Logic Design Engineer Duration: 1 Year + Location: Austin, Texas Job Description We have a need for an experienced digital logic design engineer. This engineer will assist in the design, development, and test of a digital neuromorphic accelerator chip. The selected candidate will work directly with other designers and system architects to implement ASIC logic. Task Description: The candidate must be able to perform the following tasks at start date: RTL coding of circuit, block, and top-level modules Simulation, logic debugging, and verification Timing closure Power optimization Synthesis and placement-driven synthesis Scripting Required skills/Level of Experience : At least 5 years chip design experience with functional and structural SystemVerilog Proficient at running industry standard ASIC EDA tools, including logic simulators, synthesis, timing closure, and power optimization Ability to work in an integrated team environment Ability to design from a high-level specification Nice to have skills: At least 10 years experience in any of the following: SystemVerilog, Verilog, or VHDLincluding simulation and timing closure PLEASE NOTE: The candidate must ensure compliance with Export regulations. It is preferred that CANDIDATE MUST BE EITHER A U.S. CITIZEN OR PERMANENT RESIDENT ALIEN