Job Description :
RTL Lead Engineer
Phoenix, AZ. And Bay Area, CA
Long Term

RESPONSIBILITIES

* Contribute to the development of efficient µArchitectures and contribute to ASIC digital µArchitecture, design and verification
* Understand our in-house IPs needed and how they need to be integrated, connected and verified
* Drive the top-level µArchitecture definition and develop the necessary RTL
* Drive the chip-level integration, verification plan development and verification
* Supervise the RTL-to-GDS flow and assist with synthesis and timing closure
* Support the test program development, chip validation and chip life until production maturity
* Work with FPGA engineers to perform early prototyping
* Support hand-off and integration of blocks into larger SOC environments
* Assist with Algorithm analysis, verification and improvement
* Contribute to ASIC digital architecture, design and verification
* Ability to communicate clearly

Minimum Qualifications:

* 7+ years of experience as a Digital Design Engineer and/or a Chip Lead
* Experience in RTL coding, synthesis and/or SoC Integration
* Experience in digital design µArchitecture
* BS Electrical Engineering/Computer Science or equivalent experience
*

Preferred Qualifications:

* System Verilog OVM/UVM experience
* Python (or similar) scripting experience
* Python-embedded HDL - Magma will be a preferred qualification
* Experience in SoC integration and ASIC architecture
* Experience in DFT/Testability requirement and test program definition
* Experience using High Speed interfaces like PCIe, USB, MIPI
* Master degree in EE
* Experience in AI and/or ML algorithm development will be a preferred qualification

Thanks & Regards

Mohammed Shoaib

Sage IT Inc.

Email:

Client : Accenture