Job Description :

ASIC Tech file and reference flow Developer 

The team works in close collaboration with our partners in process technology and design teams spanning CPU, Graphics, Networking, and Servers. The primary focus of the team is to accurately predict the impact of process changes on density scaling and power, performance metrics thereby facilitating quick data-based decisions for scaling and power, performance commits going from one tech node to the next

You will be working as part of a team supporting RTL synthesis and place and route experiments using internal and external vendor tools to improve Intel's product Power, Performance, and Area, for existing and future process nodes on internal Intel Architecture (IA/X86) and external ARM IP's. Candidate will be specifically expected to deal with understanding the design rules for a given technology node and translating them into corresponding technology files for SNPS Fusion Compiler and CDNS Genus/Innovus. Candidate will also be expected to work on developing and refining reference RTL2GDS flows on both SNPS and CDNS APR platforms for various technology nodes.

Minimum Qualifications:
Master of Science in Electrical Engineering + 5 years exp OR Bachelor of Science in Electrical Engineering with 7+ years of relevant experience
Experience in the following areas:
• Experience with: Perl, TCL, Shell scripting
• Experience or knowledge of ICV Coding
• Use of industry standard placement and routing CAD tools

             

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