Must Have : Advance Node Exp 3nm/5nm,Full Chip Integration, Advance/Complex SOC Integration, Cadence/Synopsys (Innovus, ICC2). Overall, 7 to 12 yrs of exp as a Physical Design Engineer.
Job Description:
- In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on Physical Design Methodologies and sub-micron technology of 7nm and lower technology nodes.
- Must have hands-on experience on PnR Suite from Synopsys/Cadence(Innovus, ICC2).
- Strong experience on Static Timing Analysis(PrimeTime - SI), EM/IR-Drop analysis (PT-PX, Redhawk), Physical Verification(Calibre).
- Understanding the practical application of methodologies and Physical Design Tools, Flow Automation and Improvements.
- Experience in complex SOC integration, Low Power and High Speed Design and Advanced Physical Verification Techniques.
- Good Customer interaction, Communication and Teamwork skills.
- Should have experience in handling >5M instance count, 1.5GHz frequency designs.
- Good to have experience on programming in Tcl/Tk/Perl to automate design process and improve efficiency.
Pls share along with skill matrix :
| Candidate Name | Years of experience | Tech Node experience | Tool experience |