Job Description :
Title: Hardware Physical Chip Design Engineer Design For Test Implementation Duration: 1 Year + Location: Austin, Texas Job Description DESCRIPTION OF PROJECT AND TASKS: Statement of Work: We have a need for a DFT expert on the Physical Design side using Cadence Design Suite. This physical design engineer will assist in the development, implementation and testing of a digital neuromorphic accelerator chip, specifically DFT. The selected candidate will work with other logic designers and system architects to implement ASIC physical design. Task Description: Candidates are expected to create/modify/script Physical Design tool flows with various DFT primitives; as well as perform spatial/physical synthesis, scan insertion, MBIST insertion, setting DFT constraints and modes, running place, route, sign-off. Candidates will be expected to act as a primary interface between Logic and Physical Design teams in the area of Design For Testability. The focus of this position is on DFT for Physical Design. Required skills/Level of Experience: Position: Senior Physical Design Engineer. Required Expertise: Experience in setting up/debugging/running DFT flows (from synthesis through Sign-off) Experience with DFT implementation and integration on the Physical Design side Multiple successful tapeouts at lower-node technologies (using FinFETs at 14nm nodes and/or below) At least 4 years experience with Cadence tools (Innovus, Genus, Modus) in the areas of physical design and DFT implementation, including physical synthesis, scan insertion, MBIST insertion, 1500 wrappers, LEC, Place and Route, Sign-off At least 3 years TCL and SHELL scripting Ideal candidates will have additional expertise in all of the following areas: Extensive experience with multiple Cadence EDA tools, tool administration, and flow automation; Synthesis (including PLE) and formal equivalence checking; RTL, gate-level and transistor-level simulations and debugging. Additional Preferred Skills: 3 years of Python/Perl scripting. PLEASE NOTE: The candidates must be able to quickly and accurately perform the following tasks: Create/tweak a simple scripted Physical Design flow for DFT, using Cadence tools on a sample RTL; this flow will include the following steps: synthesis, DFT insertion, floorplanning, power-grid creation, CTS, placement, routing, Sign-off; Implement DFT in physical design tools with all the constraint setting, false paths, functional/test modes, corners, etc. The candidate must ensure compliance with Export regulations. It is preferred that CANDIDATE MUST BE EITHER A U.S. CITIZEN OR PERMANENT RESIDENT ALIEN.