Job Description :
Port ASIC/IP RTL to Emulation platforms (Preferred: Zebu/HAPS)
Build model from released RTL .
Generate target platform loadable image(s) test and release the image to Firmware and DV teams.
Run sanity tests for qualifying release of the image(s)
Release the model to various team including Functional Validation team, Firmware, DV
Assist debug of failures providing instrumented model ( Waveform Dumps, in circuit debug) and interfacing with stakeholder.
Coordinate with Tools team to validate tool and Model release
FPGA and Emulator flows and methodologies
Basic Qualifications:
Minimum of 4 – 10 years of experience with
Daughtercards, Speedbridges, Virtual Prototyping
Hardware emulators (i.e. ZeBu/Palladium or HAPS/Protium)
Emulation Platforms & Tools, methodologies, including in-circuit emulation, hybrid systems, or simulation acceleration
Programming/scripting skills (C, C++, Python, Tcl or Perl)
Bachelor’s Degree or equivalent work experience (12 years) or an Associate’s Degree with 6 years of work experience.
Preferred Skills
Strong knowledge of Complete Design Cycle to understand the Different IP designs to integrate In the build
Simulation acceleration knowledge (DPI and Transactors)
In depth understanding of RTL and Synthesis
Logic simulation: VCS/NCSIM