Role:Design Verification Engineer
Location:Mountain View/San Jose, CA (REMOTE)
Visa Type:USC, GC, GC EAD, H1B, H4 EAD
Job Description:
• 7 -9 years of ASIC verification experience.
• Experience in System Verilog and C programming.
• Strong scripting skills (Python, Perl, Shell etc.)
• Excellent hands-on experience with IP and SOC verification.
• Excellent debugging skills using VCS and Verdi.
• Knowledge of UVM based testbench development.
• Knowledge of protocols like SPI, UART, I2C, GPIO is a must.
• Knowledge of memory protocols like HBM is a plus.
Mandatory Experience:
- Writing and maintaining test plans.
- Creating and maintaining UVM testbenches.
- Created a module testbench from scratch.
- Written Cover points, Assertions (SVA) and closed coverage.
- Knowledge of standard bus protocols such as AHB, AXI, etc.
Desirable Experience:
- Scripting and test automation for regression.
- Experience with PCIe/NVMe and/or ONFI.
- Experience with SSD architecture.