Job Description :
Validation Engineer Guadalajara , Mexico Job Description You will be part of IP design team chartered with delivering IP multiple server SOCs across Intel. Responsibilities include the following:- Define and enhance methodologies for pre-silicon validation of high complexity IP improving the overall efficiency and velocity of the pre-silicon validation team. Interact closely with the architecture and design teams, influencing product definition, implementation and validation. Create, define and develop system validation environment and test suites Responsible for the development of methodologies, execution of validation test plans, test sequences and directed tests. Skill Requirement: Education: BS/MS in Electrical or Computer Engineering with work in Digital/microprocessor Design, Computer Architecture, VLSI design, Software/Programming. This role also requires the following attributes in the candidate: 4+ years of experience as a Pre-Si Validation designer Proven track record in ASIC verification from environment development to tests development Hands-on verification experience and high-proficiency using SystemVerilog and OVM/UVM Proven track record of developing complex verification collaterals quickly and solid simulation debug skills In-depth understanding of computer architecture, PCI-Express protocols and any coherency protocols