Job Description :
ASIC Design Verification- Sr. Staff Engineer
Phoenix, AZ
Long Term
Job Description:
We are looking for SoC Design Verification Eng. to provide design verification services for multi CPU/DSP SoC.
Resp.
Testbench dev. - System Verilog UVM and C tests
Integration/dev. of C tests/APIs and SW build flow and UVM mailboxes and HW/SW communication components and of lower level UVM testbenches
Test plan dev.
Power Aware testbench dev. and simulations
Seamless porting between simulation/emulation/prototyping platforms
Regression setup and debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto
Coverage collection and closure
Working with cross functional teams (DV/Arch/Design/FW) to identify coverage scope
Min. Qualif.
Relevant exp. in RTL Design and Verification area. Exp. in SoC Design Verification and HW/SW verif.
Knowledge of System Verilog UVM and vertical testbench integration, of low level HW/SW interaction and debug, of multi CPU and debug arch., exp. with dev. of fully automated flows
Preferred Qualif.
Exp. with low level SW debug - disasm,Tarmac,trace,with coresight arc., embedded SW low level concepts and debug - Tarmac, ROM, RAM, linkers, elf, disasm, code sections, cache, security.
Exp. with coverage merging across simulation and emulation, Power Aware and Gate Level Netlist in Emulation, with dev. of fully automated flows, with Gate Level Simulations
Python Scripting
Thanks & Regards
Mohammed Shoaib
Sage IT Inc.
Email: mshoaib(AT)sageitinc(DOT)net