Job Description :
ASIC Design and Verification Engineer
We have an immediate opportunity with a large F500 client in the Roseville, CA area.
We are looking for ASIC Design and Verification Engineer at Roseville, CA with one of our major clients. Please go over the details let me know
ASIC Design and Verification Engineer
Roseville, CA
Job Type - Full time
Local Preferred
JD:
10+ years of RTL Design (Verilog) and Verification experience (SV, UVM) – combined exp
Experience on Micro architecture and interface protocols (PCIe, USB, SATA, Ethernet etc. any one)
Experience in Test planning, Test bench, environment etc.
Can do functional and code coverage
Have worked on module and top level verification for SoC
For immediate consideration please contact:
Taufeeq
UpStream Global Services.
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