I am looking for a STA/Synthesis Engineer
Job Description:
· Memory Compiler/Wrapper Script Owner with Python – needs understanding of features/requirements of SRAMs/Regfiles and able to write RTL
· Able to get critical blocks to synthesis to meet timing by using all switches within DC and feedback to RTL designers
· Expert in writing Timing Constraints from scratch and strong understanding of most SDC (Synopsys Design Compiler) commands
· someone with strong RTL experience to support the design team
· Strong topographical synthesis experience with Synopsys Design Compiler
· Strong Floorplans, DEF, Placement & Bounding experience
· Strong Timing Constraints experience with DC & PTSI
· Strong Scripting experience – Perl, Python, tcl, shell.
· Is able to read RTL and optimize for power/timing
· Nice to have P&R experience with ICC2
· Nice to have formal equivalence – Cadence Conformal/Synopsys Formality
· Nice to have memory compiler experience