Location: Boxborough, MA (Onsite)
Type: Contract
Responsibilities:
Collaborate with design and verification teams to verify complex IP blocks and subsystems.
Develop and execute test plans, testbenches, and verification environments.
Debug and resolve issues related to functionality, performance, and power.
Drive functional, code, and assertion coverage closure.
Contribute to verification strategy and methodology improvements.
Document verification plans, results, and progress for project tracking.
Requirements:
Proven experience in UVM and constrained-random simulation environments.
Strong knowledge of System Verilog, Verilog, C/C++, and scripting languages (Python, Perl, Tcl or Shell).
Solid understanding of digital design fundamentals, computer architecture, and verification methodologies.
Familiarity with 3D pipeline, GPUs, or industry graphics standards is a plus.
Experience with EDA tools (simulation, waveform analysis, coverage tools).
Excellent problem-solving, debugging, and analytical skills.
Strong communication skills with the ability to work effectively in a cross-functional team.
Self-motivated and capable of independently driving tasks to completion.
Education:
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.