Job Description :

Job Post _ ITEKJP00021697 Intel Corporation

Job Title _ Engineer: FPGA/RTL Design - II 

Location – Folsom California USA95630

Duration- 9+ Months (Probability to extend)

Hours per Week: Monday-Friday

Shift:  8 AM to 5:00PM



*** MRUNDA is required ***
Please Note -Working from home initially, and longer term flexible on working from home or office. Office preferred but not absolute requirement.
Job Description/Skills needed: RTL design engineer working on an embedded controller/subsystem. 5+ years

Experience in digital logic design with various tools and methodologies including: System Verilog, Perl, VCS/Synopsis simulators, Lint, Synthesis, Clock Domain Crossing tools, DFX Scan and Power, static timing analysis. Expert in computer architecture. The candidate must work closely w/ the Architect/u-Architect and Validation teams in determining the proper implementation strategy
for new design, define and provide feedback on specifications, develop White Box Coverage plans, understand high level IP end-to-end flows and review design code for efficiency/coverage and drive any paradigm shifts needed in correct-by-construction design implementation. Excellent communication and organization skills and ability to work in a team environment.
Minimum education: BS or MS EE or Computer Engineering, plus 5 years hands on design experience.

Client : Intel


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