Job Description :
Title: Design Verification Engineer
Location: Cedar Rapids, IA United States
Duration: Permanent Full Time

Job Description:

Main Skills:-
UVM, System Verilog
Scripting language will be plus.

This job requires candidates to work with customers and should be able to propose technical stuff and convenience customers.
Required to work with the offshore team and co-ordinate and communicate work done by them to customers, contribute individually and represent the team.

Required skills:-
B. E. /B. S. /B. Tech in VLSI/Electronics/Electrical/Computer/Instrumenta tion Engineering
Good experience or knowledgw in System Verilog HVL.
Hands-on experience of developing assertion, checkers, coverage and scenario creation.
Must have executed at-least 2-3 SoC Verification projects
Experience in developing test and coverage plan, Verification environment and validation plan.
Knowledge of industry-standard protocols (PCIe, USB, ARM, Memories
Working knowledge of C++ and building C++ test cases for system level testing
Past experience of working on a multisite project is an added advantage

Client : einfochips