Job Description :
Title: Design Verification Engg
Location Raleigh,NC
- 2+ years of experience working as a design verification engineer developing test bench components using UVM/OVM and System Verilog language
- 2+ years of experience focused on DDR protocol (timing parameters, maintenance commands, controller/PHY interactions) with a good understanding of JEDEC spec
- Experience developing agents, monitors, scoreboards, assertions, and cover points
- Experience with debugging designs as well as creating or maintaining simulation environments
- Knowledge of verification principles, testbenches, test plans, stimulus generation, and coverage

Role and Responsibilities:
- Be part of a team working on verification of DDR IPs and/or subsystems
- Define, document, and implement UVM verification environment including agents and scoreboards
- Develop and execute functional and performance verification test plans, including opportunistic use of Formal techniques
- Define and implement functional coverage and drive coverage closure
- Triage and debug testbench simulation fails.


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