Title : Senior Design Verification Engineer
Location: Bay Area, CA
Duration: Long Term
Job Description:
Responsibilities:
• Must be a quick learner, independent and communicate well.
• Knowledge and hands on experience with Verilog, System Verilog , UVM, debugging waveforms
• Building a testbench for a medium complexity block using System Verilog and UVM
• Writing random tests, directed tests, error tests & performance tests for a block of medium complexity using System Verilog and UVM.
• Developing, maintaining and supporting of the UVM verification environment.
• Debugging tests with design engineers to deliver functionally correct design blocks
• OOPS, randomization, constraints, interfaces
• Writing & analyzing functional coverage, assertions
• Generating and analyzing code coverage & writing waivers
Skills:
• SystemVerilog, UVM expertise
• Excellent Python scripting skills
• PCIe or equivalent protocol experience
• 7 years’ experience & above
• Self-starter