Job Description :

Job Title: IT|VLSI - Technical Lead I - VLSI

Start/End Dates: 2/25/2022 - 12/31/2022

Tax Work Location: USA-Milpitas-Cisco-1020_McCart

VLSI - Technical Lead

 

• Bachelor’s or Master’s degree in Electrical or Computer Engineering
• 10+ experience with ASIC Verification
• Solid understanding of Digital Design fundamentals, and Computer Architecture
• Proficiency with Verilog & System Verilog RTL coding and verification
• Good Programming/Scripting skills with languages such as Python, Awk & Perl
• Good knowledge of Object-Oriented Programming
• Problem solving skills and out-of-the-box thinking
• Strong communication skills, both verbal and written
• Team-Player, can-do attitude and will work well in a group environment while still being able to contribute on an individual basis
• Familiar with constrained random verification methodology (UVM) (required)
• Familiar with Code Coverage (desired)
• Familiar with Functional Coverage (desired)
• Knowledge of Assertion based Verification using System Verilog Assertions (required)
• Protocol knowledge in one or more of the following areas: TCP/IP, SCSI, Fibre Channel, NVMe, NVMe over Fabrics Ethernet, SAS, SATA, RDMA protocols, PCIe (desired)
• Experience with embedded CPUs, e.g. ARM (desired)
Responsibilities
• RTL verification
• ASIC test bench development
• Simulation Test Implementation
• Simulation Debugging
• Scripting
• Test plan documentation
• regressions

 

Proficiency: Advanced

• Independently execute mid sized customer projects in any field of VLSI Frontend, Backend or Analog design with minimal supervision
Expectations from this role:
1. Work as an individual contributor owning any one task of RTL Design/Module. Provide support and guidance to engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff, etc.
2. Anticipate, diagnose and resolve problems; coordinating as necessary with cross-functional teams
3. On time quality delivery approved by the project manager and client
4. Automate the design tasks, flows and write scripts to generate reports
5. Come up with novel ideas to reduce design cycle time and cost, accepted by UST Manager and client
Typical performance measures:
1. Quality –verified using relevant metrics by UST Manager / Client Manager
2. Timely delivery - verified using relevant metrics by UST Manager / Client Manager
3. Reduction in cycle time, cost, using innovative approaches
4. Number of papers published
5. Number of patents filed
6. Number of mandatory trainings attended, adhering to training goals
Performance Areas:
Outputs from this role include day to day activities on which a manager can provide feedback.
• Quality of the deliverables:
o Ensure zero bugs are present in the design / circuit design.
o Clean delivery of the design/module in-terms of ease in integration at the top level
o Meeting functional spec / design guidelines 100% without any deviation or limitation
o Documentation of tasks and work performed
• Timely delivery:
o Ensure project timelines as laid out by the client or program manager are met
o Meet intermediate tasks delivery for other team members to progress
o Calling out for help and support in the case of delay in tasks delivery
• New Skills development:
o Participate in training – skilling someone and also getting skilled in newer technologies
o Take up new areas of project development, learn on the job and deliver
• Team Work:
o Participation in team work and supporting team members at the time of need
o Able to take up additional tasks in-case of any team member(s) not available
o Able to hand hold junior team members to explain the project tasks and support to deliver
o Work dedication to go beyond the call of duty to ensure deadlines and quality are met
• Innovation & Creativity:
o Approach towards repeated work by automating tasks to save design cycle time
o Participation on technical discussion, training, forum, white paper etc
Skill Examples:
1. Languages and Programming skills:
a. System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, Makefile, Spice
2. EDA Tools:
a. Cadence, Synopsys, Mentor tool sets (one or more)
b. Simulators, Lint, CDC/RDC, DC/RTL-C, ICC/Innovus/Olympus, ETS/TK/FS, PT/Tempus, Calibre etc. (experience in one or more tools)
3. Technical Knowledge:
a. IP Spec, Architecture Design, Micro Architecture, Functional Spec, Test Plan, Verification
b. Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C, Microprocessor architecture
c. Strong Physical Design / Circuit Design / Analog Layout Knowledge
d. Synthesis, DFT, Floorplan, Clocks, P&R, STA, Extraction, Physical Verification
e. Soft / Hard / Mixed Signal IP Design, Processor Hardening, FPGA Design
4. Technology: CMOS, FinFet, FDSOI - 28nm / 22nm / 16ff / 10nm and below
5. Strong communication skills and ability to interact with team members and clients equally
6. Strong analytical, reasoning and problem-solving skills with attention to details
7. Ability to understand the standard specs and functional documents
8. Ability to deliver the tasks on-time in a quality fashion per quality guidelines and GANTT
9. Well versed with the available EDA tools and able to use them efficiently
10. Required technical skills and prior design knowledge to execute the assigned tasks
11. Ability to learn new skills in-case required technical skills are not present at a level needed to execute the project
Knowledge Examples:
1. Knowledge of project(s) in any of the design by executing – RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout, etc.
2. Understanding of the design flow and methodologies used in the designing
3. Understand the assigned tasks and have sufficient knowledge to execute the project tasks assigned by the client / manager as per known skills

             

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