Job Description :

Position:  Senior Staff Verification Engineer

Location: Campbell, CA ( 100 % remote considered)

Duration: Full Time 

DATABASE MODELING, Debug, ARM, regression, UVM, Verification Engineer, System Verilog, DV, VCS, NCSIM, X86

Seeking a seasoned Senior  Verification Engineer with a minimum of 10+ year of experience to join our verification team. Person should have prior experience with verification flows, building efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. Person will be responsible for the full lifecycle of verification, from verification planning and test execution, to collecting and closing coverage. Person should also be able to define the verification infrastructure, set up the environment and drive the Functional Verification flow.

Skills Needed:

  • Expertise is UVM  and System Verilog  is mandatory.
  • DV, VCS, ncsim, regression, debug.  
  • ASIC Verification, SoC Verification, Formal verification.
  • Develop/write testbench, develop/write tests, develop/write Functional Coverage, Assertions, Covers, property checking.
  • Collect coverage, analyze coverage.
  • Prior experience with VIP of multi-protocol Serdes.
  • Prior experience with Protocol verification such as Ethernet, PCIe, Risk 5, DDR, System Interconnect (NOC, NIC) is mandatory.
  • Prior experience in System Interconnects such as ARM, good understanding of AXI protocols.
  • Expertise leading functional verification for embedded SoC systems based on processors such as ARM, X86 or RiscV.
  • Expertise in formal verification flows and techniques.
  • Strong communication and presentation skills.
  • BSEE/MSEE is required.
             

Similar Jobs you may be interested in ..