Location: Campbell, CA ( 100 % remote considered)
Duration: Full time
DDR, PCIE, UVM, BSEE, MSEE, Protocol verification, System Verilog, Ethernet, formal verification flows
Seeking a seasoned senior Verification Engineer with a minimum of 10+ year of experience to join our verification team. Person should have prior experience with verification flows, building efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. Person will be responsible for the full lifecycle of verification, from verification planning and test execution, to collecting and closing coverage. Person should also be able to define the verification infrastructure, set up the environment and drive the Functional Verification flow.
Skills Needed
Expertise is UVM and System Verilog is mandatory.
Expertise in functional coverage flows, property checking and Assertions.
Prior experience with VIP of multi-protocol Serdes
Prior experience with Protocol verification such as Ethernet, PCIe, DDR is mandatory.
Expertise in formal verification flows and techniques.
Strong communication and presentation skills.
BSEE/MSEE is required.