Job Description :
Model development experience using System Verilog.
Good design knowledge is a must.
Emulation knowledge is required , it can be either Zebu or Veloce or Palladium.
Hands on experience in hardware description knowledge Verilog, system Verilog,
Candidates should have good Validation knowledge
Good knowledge of scripts like Perl, Python.
knowledge of Synopsys VCS, Verdi knowledge is a must