Job Description :
Title: Verification Engineer
Location: Folsom, CA
Duration: Fulltime (Permanent)

Primary Skills : Verilog OVM/UVM

Job Description:

Qualification: Bachelor/Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics
Experience: 8-12 Yrs
In depth knowledge/experience of System Verilog OVM/UVM.
Experience & good understanding of ASIC/FPGA pre-silicon verification concept i.e. focus vs full/constraint random testing, coverage based verification, testbenching, ip vs fullchip testing.
Experience in coverage points coding, SV test writing & debug, testbenching.
Explored to EDA simulation tools i.e. Modelsim/Questasim/VCS/NCsim or debug tools i.e. Verdi/Debussy.
Familiar with unix/linux environment.

Thank you,
Purushotham K, Technical Recruiter
Libsys Inc ‘IT Sharps''