Job Description :
FPGA Design and Debug Leads
BSEE or MSEE with 4+ years of experience
Has relevant project experience in logic design, SoC architecture, RTL coding or design verification.
Creation of Emulation/Field Programmable Gate Array (FPGA) models from a RTL design using emulation/FPGA synthesis, partitioning and routing tools.
Experience in compiling designs to load FPGA emulation platform.
Familiarity with Verilog/System Verilog /VHDL/C and Verification methodologies (UVM,OVM)
Good FPGA debugging skills
Working knowledge of high speed interfaces is a plus(any of PCIe-gen3, USB, DDRx or similar protocols)