Job Description :
Role: Physical Design Engineer
Duration: +12 Months
Location: Sunnyvale,CA

Job Requirements:
EE degree (MSEE preferred) with 8+ years of overall design experience, preferably with high speed multi-gigabit SerDes PHY designs or other high performance IP designs
Experience in automated synthesis and timing driven place and route of RTL blocks (Verilog experience preferred) for high speed datapath and control logic applications
Experience in automated design flows for clock tree synthesis, clock and power gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction
Strong background in digital circuit techniques, efficient and robust implementation.