Job Description :
Job Description:
Develop pre-Silicon functional validation tests in Gate Level environment and Test benches to verify system will meet design requirements.
Create test plans for RTL and Gate Level Simulations(GLS) validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL/GLS tests. Analyze and use results to modify testing.

Assignment will include but not be limited to:
- Validating designs at block or full-chip level by authoring validation plans, writing focus tests, developing and analyzing coverage monitors, creating event injectors, writing architectural and micro-architectural correctness checkers, running functional simulations, and debugging failures
- Maintaining and enhancing the validation infrastructure by creating new tools to support validation.
- Working in a very team-oriented environment and interacting with engineers from other design disciplines.

Required Skills:
- Bachelor''s in Electrical Engineering, Computer Engineering, Computer Science or related discipline
- 10+ years of experience in the area of hardware design and verification
- 10+ years of pre-si verification work using a validation methodology such as OVM, Specman E, System Verilog, Synopsys VCS, with special emphasis on GLS.
Perl scripting experience a must.

Any experience with fault injection tools a plus.