Job Description :
-Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing analysis and closure, verification, and system integration
-RTL coding and simulation in VHDL or Verilog
-Test bench development for the verification of RTL blocks using VHDL or System Verilog
-Recommend new tools and practices for continuous improvement in the group''s ASIC / FPGA design flow

This position requires these skills and abilities:

-RTL coding and simulation in VHDL or Verilog OR Test bench development for the verification of RTL blocks using VHDL or System Verilog
-Digital circuit architecture, design, resource tradeoffs, timing analysis and timing closure
-Proficiency using ASIC and/or FPGA simulation and synthesis tools (e.g. Questasim, Synplify, FPGA-specific tools)
-Familiarity with revision control concepts and tools (e.g. Clear case, Subversion)
-Ability to work with minimal supervision, part of a team of engineers with a variety of skills and backgrounds, matrixed into projects with aggressive schedules and frequent milestones
-Strong oral and written communication skills and the ability to document and present one''s work and status
-Ability to obtain a Security Clearance. US Citizenship is required.
-Bachelor''s Degree in applicable engineering field

Desired skills of a successful candidate:

-Familiarity with best practice chip-level verification techniques and languages (e.g. constrained random, functional coverage, System Verilog)
-ASIC / FPGA lab validation with advanced lab equipment
-Design for Test (DFT) and manufacturability issues
-Experience with Unix, scripting, C/C++, and/or Perl

Client : Rockwell Collins