Job Description :
Experience in FPGA design
Verilog HDL RTL coding
Experience in Xilinx Vivado tools
Experience in Xilinx, Xilinx Zynq, Altera devices
Experience in OTN, PCIe, Ethernet, DDR, AXI protocols
Experience with timing closure on 300/400 Mhz clocked designs.
Conversant with Tcl scripting for lab verification a plus.
             

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