Job Description :
Title : PCIe Gen3/4 Verification Engineers

Location : California City, CA

Job Type: Full-time

Required experience: Pcie Verification: 1 year

Requirements:

3-12 years of experience in ASIC/IP functional Verification Engineer

Strong expertise in all layers of any of the following protocol PCI-Express Gen 3 / 4

Strong UVM skills in terms of UVM testbench infrastructure development, test creation (including writing assertions) and test debug etc.

Good domain skills in the areas of PCIE, DDR, HBM, NOC, DSP etc.

Strong verification failure debugging skills using Verdi or other debuggers.

Experience developing UVM, System Verilog components from Scratch

Good experience in developing test plan covering 100% of protocol features

Sound debugging skills

U.S. Citizens and those authorized to work in the U.S. are encouraged to apply

Job Location: Bay Area, CA Experience: 3 to 12 years Educational Qualification – BSEE/MSEE Authorized to work in US.
             

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