Job Description :
Hi,
Hope you are doing well, My name is Ravi and I''m from Enterprise Solutions, Inc. I came across your resume on a job board and wanted to check if you are available for a project. If you are available, interested, planning to make a change, or know of a friend who might have the required qualifications and interest, please call me at, and send me your updated resume and below mentions Details at
JOB SPECIFICATION: - (Please ignore if not a good match)
Job Title: Performance modeling and RTL correlation engineer
Location: Santa Clara, CA
Duration: Contract
Overview:
The infrastructure IP group consists of a multi-disciplinary group involved from early product specification and analysis effort to final core delivery to the SoCs. Ideal candidates should have strong performance model development skills, expertise in creating test-benches and verifying RTL designs as well as exposure to memory system concepts like DRAM controllers, cache controllers and interconnects. The successful applicant will be responsible for developing and correlating performance models for memory system IPs. Ideal candidates should be self-starters and have the ability to debug and triage both model and RTL source code issues.
Minimum Qualifications:
Experience with the following: - Expertise in Object oriented programming and general SW debug (C++)
Experience with SystemC and transaction-level modeling (TLM - Advanced verification methodology like system Verilog-OVM or system Verilog UVM.
Test planning and test bench development skills - Ability to summarize performance data and communicate issues effectively.
Strong skills in scripting (perl/python)
Strong working knowledge of modeling tools and techniques
Preferred Qualifications:
Exposure to interconnect, cache and memory controller verification is a plus.
Experience with data analysis using Excel, JMP, etc.
Education Required:
Bachelor''s, Computer Engineering and/or Electrical Engineering Preferred: Master''s, Computer Engineering and/or Electrical Engineering
Comments :only submit candidates that can start within 0-3 weeks 11/29 - notes from supplier call: • Not a test bench architects • 3-4 years'' experience ok • Understand system C modeling and RTL design • Object oriented programming (OOP) • Performance memory controllers • Performance analysis of interconnects and/or memory controllers • C++ • OVM/UVM • No VHDL experience required
Primary Skills:
SV, UVM,C++, Verilog/VHDL, TLM, System C, performance Modeling