Job Description :
Position:
DFT Engineer
Location:
San Diego, CA
Duration and Shift:
24 months (Possible Extension)
Job Overview: Digital ASIC Design
Team is currently seeking candidates for a senior position responsible for the implementation of advanced DFT/DFD(design for test/design for debug) techniques for low power, high performance and highly integrated SoCs including CODEC and high-speed PHY & SerDes systems. The successful candidate will help in the deployment of DFT methodologies that reduce test cost, increase production quality and enhance yield learning.
Minimum Qualifications:
* Bachelor''s degree in Electrical or Computer Engineering plus experience with the following:
* DFT/DFD techniques for high performance processors
* Ccore-based test methodology and scan isolation
* Fault modeling Stuck-at, Transition, Path Delay, Gate Exhaustive, IDDQ, and other advanced DFT models
* JTAG, MBIST, Scan Compression, ATPG, Fault Simulation and at-speed testing
* Industry ATPG tools: Mentor Fastscan, Synopsys Tetramax, or Cadence Encounter Test ATPG tools
* Synopsys DFTC scan insertion - Logic Design, VHDL, Verilog RTL, verification, and static timing analysis
* One or more of the following languages: C, C++, TCL or Perl
* Industry simulation tools such as VCS, Modelsim, or others
* Silicon bring-up, debug, and validation of DFT features on ATE (automatic test equipment)
Preferred Qualifications:
* Experience in Mentor tools for ATPG and Coverage Analysis.
* Experience with formal verification tools such Verplex, Formality, etc.
* Knowledge and experience of timing closure and industry tools like PrimeTime and PTSI
* Experience with other industry tools such as Vera, Spyglass, 0-in, Jasper, RedHawk, PrimePower
Education:
* Required: Bachelor''s, Electrical Engineering
* Preferred: Master''s, Electrical Engineering or equivalent experience