Design Verification Engineer

Santa Clara, CA Santa Clara CA 95056

Date : May-15-17

Design Verification Engineer

Santa Clara, CA

May-15-17

Work Authorization

US Citizen
GC
H1B
GC EAD

Preferred Employment

Corp-Corp
W2-Permanent
W2-Contract
1099-Contract
Contract to Hire

Job Details

Experience

:

Senior

Rate/Salary ($)

:

DOE

Duration

:

18 Months

Sp. Area

:

DBAs

Sp. Skills

:

x-Other

Permanent Direct Hire

Consulting / Contract

H1B OK

Direct Client Requirement

Required Skills :

System Verilog OVM/UVM VCS

Preferred Skills :

• Testbench (test sequence, BFM, interface, generators, scoreboards, monitors, etc) • Assertion coding

Domain :

IT/Software

Work Authorization

US Citizen
GC
GC EAD
H1B

Preferred Employment

Corp-Corp
W2-Permanent
W2-Contract
1099-Contract
Contract to Hire

Job Details

Experience

:

Senior

Rate/Salary ($)

:

DOE

Duration

:

18 Months

Sp. Area

:

DBAs

Sp. Skills

:

x-Other

Permanent Direct Hire

Consulting / Contract

H1B OK

Direct Client Requirement

Required Skills :

System Verilog OVM/UVM VCS

Preferred Skills :

• Testbench (test sequence, BFM, interface, generators, scoreboards, monitors, etc) • Assertion coding

Domain : IT/Software

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Certec Consulting, inc.
Arlington, IL
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Job Description :

Job title and Exp. :

Pre-Si Validation Engineer/Design Verification , 3-5 years or more

JD:
System Verilog
OVM/UVM
Testplan
Testbench (test sequence, BFM, interface, generators, scoreboards, monitors, etc)
Assertion coding
Functional Coverage coding and closure
Code Coverage closure
Low power coverage
VCS NLP

Client : Intel

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