Job Description :
Verification Engineer
Location : Santa Clara, CA
Duration : 1 Year +
We need only US Citizen/GC/EAD. No H1B here.
Central to our mission is a highly programmable chip. As part of the verification team, you will be responsible for independently creating leading-edge constrained-random verification environments and using them to drive functional correctness of innovative SoCs.
This position is in Santa Clara, California.
Skills, Education, and Experience Required
BS and/or MS in Computer Science or equivalent degree
8+ years of experience in ASIC/SoC verification with SV/UVM environments
In-depth knowledge of verification flows Clear understanding of constrained random verification process, functional coverage, code coverage, assertion methodology and philosophy
Team player with excellent communication skills and the desire to take on diverse challenges Additional Success Factors
Advanced knowledge of CPU and SoC architecture/design
Experience in verifying data center protocols such as Ethernet, TCP/IP and other communication protocols
Knowledge of formal verification, hardware emulation
Experience with security
Startup experience Keywords silicon, chip, SoC, ASIC, processor, CPU, GPU, fabric, networking, SSD, architecture, design, verification, CAD tools, x86, ARM, MIPS