Job Description :
Hello,
There is an excellent job opportunity.
Please find the details below regarding the same.
Please let me know if you are interested in pursuing this opportunity and send me your updated resume.

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Verification Engineer
Experience From: 10-20 Year(s)
Duration: 3 Month(s) but is usually extended up to 2 years
State: San Jose CA
Interview Mode: Telephonic, Skype

Required Hands-on Experience:
Embedded system Verification methodology
General DV concepts on CPU sub-system and peripheral/CPU HW/SW development flow
C/Assembly, Verilog and system Verilog languages
Strong debugging skills on tools like Verdi, VCS and DVE
Strong test bench modeling experiments in sensing field
Deep knowledge on I2C/SPI, memory interfaces
Deep knowledge on SCAN/mBIST flow, and mixed signal simulation requirements.
Deep knowledge on coverage analysis, rich experience on SVA or PSL it is preferred that candidate has experience on static/formal verification flow e.g. clock domain crossing, reset domain crossing
CPU/system verification experience with knowledge on C/assembly language and firmware tool chain setup
Experience on Cadence Conformal/Synopsys Spyglass (Atrenta)/Mentor Questa tool and be familiar with clock domain crossing verification method
Rich experience on Coverage-Driven Verification Methodology or SVA