Job Description :
Professional Knowledge:
8+ years of hands-on verification experience using System Verilog and OVM/UVM.
Strong understanding of engineering design principles.
Proven track record in ASIC verification from environment development to tests development.
Excellent written and verbal communication skills.

Responsibilities:
Create pre-silicon verification test plans.
Develop the architecture and design of the verification environment in OVM/UVM.
Develop/run/debug tests and functional coverage in System Verilog.
Mentor other engineers in using the verification infrastructure and creating test benches.

Requirements:
BS in EE or Computer Science, Master’s preferred.
Experience with creation of plans, schedules and cost estimates for design verification efforts.
Experience with implementation of modern verification environments that include use of constrained-random stimulus and use of functional coverage.
Proficiency in System Verilog.
Experience with OVM/UVM.
Proficiency in scripting languages and utilities including Make, Perl, Python, etc.
Expert level knowledge of simulation tools such as VCS from Synopsys.
Experience in network ASIC design verification is a plus, (ex: Ethernet, PCI-Express, InfiniBand, SONET)

Client : Semiconductor Giant