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Verification Engineer - IV
Hudson, MA
Hudson
MA
01749
Date
: Jan-06-17
2017-01-06
2018-01-06
Verification Engineer - IV
Hudson, MA
Jan-06-17
Work Authorization
US Citizen
GC
H1B
EAD (OPT/CPT/GC/H4)
Preferred Employment
Corp-Corp
W2-Permanent
W2-Contract
1099-Contract
Contract to Hire
Job Details
Experience
:
Senior
Rate/Salary ($)
:
Market
Duration
:
3 Months to start with Possible Extension
Sp. Area
:
Others
Sp. Skills
:
Others
Consulting / Contract
CONTRACTOR
Required Skills
:
VERIFICATION, SYSTEM VERILOG, VERILOG, OVM/UVM, OVM, UVM, Pre-Silicon, Pre-Si, ASIC verification, Perl, Python, simulation, VCS, Synopsys, Ethernet, P
Preferred Skills
:
Domain
:
IT/Software, Manufacturing
Work Authorization
US Citizen
GC
EAD (OPT/CPT/GC/H4)
H1B
Preferred Employment
Corp-Corp
W2-Permanent
W2-Contract
1099-Contract
Contract to Hire
Job Details
Experience
:
Senior
Rate/Salary ($)
:
Market
Duration
:
3 Months to start with Possible Extension
Sp. Area
:
Others
Sp. Skills
:
Others
Consulting / Contract
CONTRACTOR
Required Skills
:
VERIFICATION, SYSTEM VERILOG, VERILOG, OVM/UVM, OVM, UVM, Pre-Silicon, Pre-Si, ASIC verification, Perl, Python, simulation, VCS, Synopsys, Ethernet, P
Preferred Skills
:
Domain
:
IT/Software, Manufacturing
Intelliswift
Newark, CA
Post Resume to
View Contact Details &
Apply for Job
Job Description
:
Professional Knowledge:
8+ years of hands-on verification experience using System Verilog and OVM/UVM.
Strong understanding of engineering design principles.
Proven track record in ASIC verification from environment development to tests development.
Excellent written and verbal communication skills.
Responsibilities:
Create pre-silicon verification test plans.
Develop the architecture and design of the verification environment in OVM/UVM.
Develop/run/debug tests and functional coverage in System Verilog.
Mentor other engineers in using the verification infrastructure and creating test benches.
Requirements:
BS in EE or Computer Science, Master’s preferred.
Experience with creation of plans, schedules and cost estimates for design verification efforts.
Experience with implementation of modern verification environments that include use of constrained-random stimulus and use of functional coverage.
Proficiency in System Verilog.
Experience with OVM/UVM.
Proficiency in scripting languages and utilities including Make, Perl, Python, etc.
Expert level knowledge of simulation tools such as VCS from Synopsys.
Experience in network ASIC design verification is a plus, (ex: Ethernet, PCI-Express, InfiniBand, SONET)
Client :
Semiconductor Giant
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