Job Description :
Project Details
Role : Validation Engineer
Location : Santa Clara, CA
Duration : 6+ Months
Mode of Interview : Telephonic, Face to Face
Description
Senior FPGA Design Verification Engineer
Responsibilities:
§ Own the design verification of the FPGA chips and its functional blocks
§ Test Plan ownership and coordination with Architecture, Design, DFT and other teams to deliver
a complete and comprehensive verification plan
§ Ownership of system, chip, and IP models for verification
§ Evaluation and selection of flows and EDA tools
§ Development and deployment of processes and flows for Design Verification.
Qualifications:
A Master or BS degree in EE/CS with 10+ years of industry experience in ASIC/FPGA design
verification
Hands-on experience in the entire verification process, from test plan to block and system level
simulation, using standard EDA tools (Cadence Incisive suite and/or Mentor Questa)
Experience with Universal Verification Methodology and tools
Hands-on experience with Block level and System level tests writing for FPGA / ASIC designs
Experience with code coverage methodology
Domain expertise in standard bus protocols: PCIe, SPI, I2C, LVDS
FPGA-based co-simulation, and emulation platforms for Design Verification
Working knowledge of SystemVerilog & Object-Oriented techniques
Scripting languages such as Python, Perl, Shell
Solid debugging and problem-solving skills