Job Description :
System Integration Design Verification Engineer
Job Location: Andover, Massachusetts, United States
Duration: Full time
Job Description
Client., is a leading provider of next-generation ultra-broadband distributed and virtualized architectures in mobile, fixed telecom and cable networks. As the original supplier of commercially deployed CCAP systems that delivers voice, video, and data over a single port, Client continues a tradition that brings leading edge solutions to hundreds of service providers around the world.
We are seeking to hire a self-motivated, team-oriented senior networking System Integration Design Verification Engineer to join our Hardware Engineering team located in Andover, MA, USA, facility is 30 minutes North of Boston.
The System Integration Design Verification Engineer will participate in the verification effort. This individual will be a key member of the FPGA system, full chip, and block level verification team and will be responsible for developing the verification environment; developing test plans and verifying the function of the FPGA.
ESSENTIAL DUTIES & RESPONSIBILITIES:
Hands-on implementation work for every aspect of FPGA design verification, working closely with the system group, architects, RTL designers and verification teams developing the verification flow and methodology, test bench, and test cases, plus executing the test plan, working closely with the design team to ensure the highest design quality.
Create, evaluate and enhance test plans to increase test coverage.
Run regression.
QUALIFICATIONS:
Proficient experience using ARM process is required.
Bachelor’s degree in Electrical Engineering, Computer Engineering or Computer Science; or equivalent work experience required; MS preferred.
Minimum of 5+ to 7 years of FPGA design verification experience with a proven track record of successfully verifying and delivering complex FPGAs.
Experience in going through several complete and successful FPGA design/verification cycles from architecting and creation of FPGA test environment to release to customer.
Possesses a full understanding of design using Verilog, and working experience with "C".
Strong leadership/communication/interpersonal skills required.
Test bench design and implementation.
Coverage specification and analysis.
Reference model design and implementation.
Automation of the regression test suite.
System Verilog, or equivalent object oriented verification environment.
Solid verification skills: planning, problem solving, debugging, random testing, adversarial testing required.
Experience in DSP based FPGA designs is highly desirable.
Looking forward for your response.