Job Description :
Please note:
Genesys tool experience required, 10nm process preferred.

Able to perform a - Variety of Technical and non-repetitive tasks associated with all phases of chip Iayout development, up to and including Unit and Chip-Level Iayout mask design.
Must possess strong Iayout design skills, particularly in digital design methods and concepts.
Can develop and maintain Iayout schedules.
Must be able to plan, draw, assemble and - Verify highly complex Fubs or units.
Able to utilize and follow physical and electrical design rules.
The candidate must be knowledgeable and have experience using the Cadence editor.
*Two year Technical degree and 8+ years of directly related expereince.