Job Description :
Role: Logic Design Lead
Location: Sunnyvale , CA
Duration: Full time
Job Description:
· 9+ years of experience and Participated in 2-3 SoC projects
· Must have extensive experience in Micro-architecture design at IP/Subsystem level
· Experience in any of the following domain is highly desirable:
o HBM
o PCIe – Gen3/4
o Any high speed chip to chip interconnect
o Multi core processor architecture and SIMD processors
· Extensive experience in SoC RTL coding (Verilog or System-Verilog
· Experience in RTL Code Linting and CDC checks.
· Experience in RTL integration using Industry standard tools, is an added advantage
· Experience in low power design techniques
· Good understanding of DFx design techniques
· Experience in creating and understanding of Design Constraints (SDC files-Clock Freq, Clock Groups, MCP, False Path, Exceptions)