Job Description :
Logic Verification Engineer - GCH/USC
San Jose, CA - Locals to Bay Area Only
12 Months

Job Description: We are looking for individuals to fill positions for Logic Verification Engineers

Candidates must have experience performing ASIC Verification based on architectural/micro-architectural specification review and analysis followed with definition of Verification requirements.

Skill sets required, not limited to the following:
A strong background in specifying and developing random test bench environments
Strong background in System Verilog, VMM/UVM and C/C++
Strong understanding of Hardware Design, Verification and Validation Principles
Strong experience with Verilog and System Verilog design of complex IP blocks working with high speed design.

Strong background in the following verification disciplines: test bench architecture, test case development, functional coverage, coverage collection and analysis
Demonstrated ability to create and document verification plans
Experience with high-speed transceiver protocols PCI Express is must and UPI
Experience with high-speed memory protocols including DDR3/4, QDR and HBM2
Experience with microcontroller subsystem verification
Experience with formal verification methods property checking
Experience verifying design-for-test DFT logic
Strong verbal and written communication skills

Educational requirements for this position: BSEE/CE minimum, MS preferred plus 5-10 years of experience in ASIC Logic Functional Verification

Preferred skills:
Strong background in design verification, Knowledge of UVM based methodologies preferred