Swana Solutions LLC
Edison, NJ
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Job Description :
Location :: Dallas,Texas
Contract Duration: 6 Months
Experience: 4+ years FPGA design experience

· Conversant in Verilog

· Conversant with Xilinx tools – Vivado

· Experience with timing closure on 300/400 MHz clocked designs

· Conversant with Tcl scripting for lab verification
* Experience with programming and a working knowledge of one or more RTL languages
such as VHDL, Verilog/System Verilog, and experience with RTL synthesis and simulation
tools. Familiarity with scripting languages such as TCL.

Skills :

Verilog, System Verilog, Vivado, Xilinx, OVM, Ethernet, SONET or OTN, TXCVR or SERDES.
Comfortable working in LAB, as designs need verification.


Possible Assignments:

· FPGA design

· Test point development

· Implementation/coding/lint

· Module Level Simulation

* Chip Level Simulation