Job Description :
This role will require candidates to develop and integrate the current and future RTL designs into a UVM environment.
Candidates will need to create reports providing coverage and testing results to the teams to help troubleshoot issues in the design.
This role may also require creating behavioral models of the design and developing RTL which will be integrated into the testing environment.
Knowledge of Packet Monitoring a plus. Exposure of Verilog and SystemVerilog